Keysight Technologies has introduced its new Chiplet PHY Designer 2025, a solution designed for high-speed digital chiplet design specifically tailored to artificial intelligence (AI) and data centre applications.
The enhanced software platform supports the latest interconnect standards, including Universal Chiplet Interconnect Express (UCIe) 2.0 and the Open Compute Project's Bunch of Wires (BoW). This support forms part of Keysight's Electronic Design Automation (EDA) standards-based approach, aiming to facilitate pre-silicon validation and streamline the design process towards tapeout.
As AI and data centre chip technology advance, effective communication between chipsets is crucial for performance optimisation. Emerging standards such as UCIe and BoW address this demand. These standards define the interconnects among chiplets within advanced 2.5D/3D or laminate/advanced packages. Designers who embrace these standards and verify compliance contribute to a more cohesive ecosystem, thereby minimising development costs and risks.
The Chiplet PHY Designer 2025 ensures interoperability by verifying that designs comply with UCIe 2.0 and BoW standards. This verification enables seamless integration across advanced packaging ecosystems, vital for maintaining design integrity.
The new solution accelerates time-to-market by automating simulation and compliance testing setups, such as the Voltage Transfer Function (VTF). This automation simplifies chiplet design workflows, allowing designers to bring products to market more quickly.
The software improves design accuracy by providing insights into signal integrity and bit error rate (BER) and offering crosstalk analysis, which reduces the risk of costly silicon re-spins. It also optimises clocking designs by supporting advanced clocking scheme analysis, such as the quarter-rate data rate (QDR), for precise synchronisation in high-speed interconnects.
Hee-Soo Lee, High-Speed Digital Segment Lead at Keysight EDA, commented, "Keysight EDA launched Chiplet PHY Designer one year ago as the industry's first pre-silicon validation tool to provide in-depth modelling and simulation capabilities. This enabled chiplet designers to rapidly and accurately verify that their designs meet specifications before tapeout. The latest release keeps pace with evolving standards like UCIe 2.0 and BoW while delivering new features, such as the QDR clocking scheme and systematic crosstalk analysis for single-ended buses."
"Engineers using Chiplet PHY Designer save time and avoid costly rework, ensuring their designs meet performance requirements before manufacturing. Early adopters, like Alphawave Semi, attest that Chiplet PHY Designer ensures seamless operation and interoperability for 2.5D/3D solutions available to their chiplet customers."
Keysight will demonstrate the capabilities of Chiplet PHY Designer at DesignCon, showcasing the software at its booth in the Santa Clara Convention Center at the end of January 2025.
